The present manual contains tables of instruction latencies, throughputs and micro-operation breakdown and other tables for x86 family microprocessors from Intel, AMD and VIA.
The figures in the instruction tables represent the results of my measurements rather than the official values published by microprocessor vendors. Some values in my tables are higher or lower than the values published elsewhere.
The discrepancies can be explained by the following factors:
Most values are the same in all microprocessor modes (real, virtual, protected, 16-bit, 32-bit, 64-bit). Values for far calls and interrupts may be different in different modes. Call gates have not been tested. Instructions with a LOCK prefix have a long latency that depends on cache organization and possibly RAM speed. If there are multiple processors or cores or direct memory access (DMA) devices then all locked instructions will lock a cache line for exclusive access, which may involve RAM access. A LOCK prefix typically costs more than a hundred clock cycles, even on single-processor systems. This also applies to the XCHG instruction with a memory operand.
|Description :||Download free Instruction tables, Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs, PDF file by Agner Fog.|
|Created :||May 2, 2016|
|Size :||809.15 KB|
|File type :|
|Author :||Agner Fog|
|Evaluation:||4.5/5 Total des votes : 6|
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